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By Strassman S.

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The wafer on the left has 7 bad die out of a total of 37; the yield is 30/37, or 81%. The wafer on the right with a smaller die size also has 7 bad die, but the yield is 81/88, or 92%. A yield of 92% is economically viable, but 81% is probably not. The underlying causes for bad die may be broadly classified as processing variations and point defects. Processing variations in doping, oxide thickness, metal thickness, or epitaxial layer thickness can result in nonworking devices or circuits that do not meet the required electrical specifications.

The high failure rate near the end of life is due to wear-out. In the case of integrated circuits, wear-out may be eliminated almost entirely. Various probability density functions have been used to model integrated circuit failure. The simplest is the exponential model, which results from a constant failure rate per device. 8 1 FIT = 1 failure in 109 device hours. 24) and MTTF = 1 . 25) Failure rates are measured in FITs (Failure unITs): 1 FIT = 1 failure . 1 year. A failure rate less than 10 FIT is very desirable, whereas 1000 FIT would be unacceptable in a complex system.

Fm Page 12 Monday, November 10, 2003 9:55 AM 12 Digital Integrated Circuits: Analysis and Design VDD I DDL VDD GND . 13 Determination of PL (the output low power). 4 Dissipation Power dissipation is an important consideration for nearly all applications of digital integrated circuits. In portable devices, the power dissipation must be minimized to prolong battery life. For all digital equipment, portable or stationary, the power dissipation must be minimized because of the associated heat that must be removed.

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